The present invention relates to semiconductor devices and methods for fabricating the devices, and more particularly relates to a MIS semiconductor device which can be reduced in size and has a doped layer having a shallow junction depth and a low resistance, and to a method for fabricating the semiconductor device.
As the number of devices included in a semiconductor integrated circuit continues to increase, MIS transistors are required to be further reduced in size. To that end, MIS transistors need to have a channel doped layer having a shallow junction depth and a low resistance (see Japanese Laid-Open Publication No. 2002-33477, for example.)
Hereinafter, with reference to the accompanying figures, it will be described how to fabricate a semiconductor device including a conventional MIS transistor.
FIGS. 13A through 13E indicate process steps for fabricating the conventional semiconductor device.
First, as shown in FIG. 13A, ions of indium (In) as a P-type dopant are implanted into a semiconductor substrate 100 made of P-type silicon, and then ions of boron (B) as a P-type dopant are implanted into the semiconductor substrate 100. Thereafter, a heat treatment is performed, whereby a P-type channel doped layer 103 is formed in the upper portion of the semiconductor substrate 100 by the diffusion of the indium ions, and a P-type well 104 is formed under the P-type channel doped layer 103 by the diffusion of the boron ions.
Next, as shown in FIG. 13B, a gate insulating film 101 made of silicon oxide is selectively formed on the principal surface of the semiconductor substrate 100, and a gate electrode 102 made of polysilicon is selectively formed on the gate insulating film 102.
Subsequently, as shown in FIG. 13C, with the gate electrode 102 used as a mask, arsenic (As) ions are implanted into the semiconductor substrate 100 to form N-type extended implantation layers 106A. Then, with the gate electrode 102 used as a mask, ions of boron (B) as a P-type dopant are implanted into the semiconductor substrate 100, thereby forming P-type pocket implantation layers 107A under the N-type extended implantation layers 106A.
Then, as shown in FIG. 13D, an insulating film made of silicon oxide is deposited on the semiconductor substrate 100 to cover the gate electrode 102. The deposited insulating film is then etched anisotropically, thereby forming sidewalls 108 on both lateral faces of the gate electrode 102.
Next, as shown in FIG. 13E, the gate electrode 102 and the sidewalls 108 used as a mask, ions of arsenic as an N-type dopant are implanted into the semiconductor substrate 100. Thereafter, the semiconductor substrate 100 is heat-treated at a high temperature of about 1050° C. for a short time, thereby forming N-type heavily doped source/drain layers 105 in the semiconductor substrate 100 alongside the respective sidewalls 108. In this process step, N-type extended doped layers 106 are formed in the semiconductor substrate 100 between the N-type heavily doped source/drain layers 105 and the P-type channel doped layer 103 by the diffusion of the arsenic ions contained in the N-type extended implantation layers 106A. Also, P-type pocket doped layers 107 are formed under the N-type extended doped layers 106 by the diffusion of the boron ions contained in the P-type pocket implantation layers 107A.
As described above, in order to reduce the size of the transistor without causing short channel effects to be exhibited, the conventional semiconductor-device fabrication method tends to use indium-ion implantation in forming the P-type channel doped layer 103 so as to obtain a channel structure having steep concentration profiles.